Systems including electronic, magnetic, vibrating, and optic subsystems can be formed on a substrate. An important class of system malfunctions includes failures caused by unexpected coupling of otherwise unrelated signals. For example, in the conventional integrated circuit, unrelated signals occur simultaneously in different portions of the circuit. Circuit design and fabrication processes as well as process variations may cause circuit malfunction due to unexpected coupling of signals. A transition of one signal may couple into an otherwise unrelated signal or the state of several signals may decrease the noise immunity of an otherwise unrelated signal. Such coupling may be due to physical proximity of circuit features, unexpected simultaneous operations, unexpected variation in dimensional tolerances, and variation in fabrication steps such as mask alignment and resolution.
Analogous failures arise in systems formed on a substrate based on magnetic, vibration, and optic principles. Currently, the most sophisticated test methods are for systems of a class including integrated circuits.
Integrated circuits are tested by applying a pattern of signals to the inputs and observing the output signals. For digital logic circuits, a lengthy binary pattern is used. Such a test pattern includes portions designed to exercise circuits that are in physical proximity to assure detection of failures related to unexpected coupling. Pattern length increases when testing many combinations of possible interactions between signals and circuit functions. As test patterns become longer, the time required to perform the test becomes longer as well.
In the typical digital integrated circuit tester, the test pattern to be applied to a device under test is organized as a list of test vectors. Each vector has at least one bit position associated with each pin on the device. Vectors may be for stimulus, for response comparison, or for a combination of both. The number of vectors associated with a pin is called the pattern depth. Conventional testers permit several hundred pins per vector and a pattern depth of several thousand states. Although these quantities seem large in the abstract, complex circuits (especially memory devices) may require many millions of vectors for a thorough test. Memory testers employ pattern generators to simplify pattern definition without sacrificing pattern sophistication.
The most sophisticated test patterns are those required for digital circuits having several complex functions that are intended to operate asynchronously to each other. Examples of such circuits include microprocessors having operation of the arithmetic logic unit independent from operation of an I/O bus management unit and video memories having operation of a low speed parallel random access port independent from a high speed serial access port. Such devices are tested efficiently on costly specialized testers.
The cost of testing is a significant portion of manufacturing costs. Digital integrated circuit testers (especially memory device testers) initially cost several millions of dollars and have significant calibration and maintenance expenses. The useful life of such a tester is limited by its design--the number of pins, pattern depth, and signal generating and comparison speeds. These and other factors limit the number of applications the tester can perform due to changes in integrated circuit packaging technology, increasing signal speeds, increasing disparity of signal speeds, and the increasing number of functions designed into a single integrated circuit package. In addition to equipment related costs, manufacturing costs include labor costs related to the duration of tests and the number of devices that can be tested simultaneously.
Tests which require many hours per test article are among the most costly. Environmental tests and burn-in tests typical of integrated circuit testing include a large number of devices under test simultaneously. Such tests may be conducted for days or weeks in which continuous electrical functional testing is desired or required. Economic and practical constraints limit pattern length and the amount of test equipment dedicated to these tests.
Reductions in test cost and improvements in test effectiveness have been made for systems other than systems formed on a substrate. When testing rack-mounted electronic systems at the subassembly (box) level and at the circuit card level, it is conventional to incorporate test circuits within the subassembly under test and circuit card under test to reduce the amount of external test equipment dedicated to the test.
Improvements to test effectiveness for digital integrated circuits have focused on synchronous testing. To achieve high test rates, integrated circuit testers synchronously use random access memory per pin in the tester and synchronously use pattern generators in the tester. It is conventional to form on substrates test circuits that monitor circuit functions and synchronously exercise circuit functions. However, such conventional techniques and monitoring circuits do not exercise circuit functions in a manner to detect failures due to asynchronous coupling of unrelated signals.
Thus, there remains a need for improving the efficiency of testing for systems formed on a substrate. The need is most visible currently for integrated circuits testing, though analogous systems have foreseeable analogous test needs. In addition, there remains a need for decreasing costs related to testing and improving the thoroughness of testing. Further improvement can be gained by employing methods of the present invention and incorporating circuits of the present invention in the design of systems formed on a substrate.